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| power management 1 www.semtech.com sc1405c high speed synchronous power mosfet smart driver features applications revision: january 13, 2004 typical application circuit description the sc1405c is a dual-mosfet driver with an internal overlap protection circuit to prevent shoot-through. each driver is capable of driving a 3000pf load in 15ns rise/ fall time and has ultra-low propagation delay from in- put transition to the gate of the power fet?s. adaptive overlap protection circuit ensures that the synchronous fet does not turn on until the top fet source has reached a voltage low enough to prevent shoot-through. the de- lay between the bottom gate going low to the top gate transitioning high is externally programmable via a ca- pacitor to minimize dead time. the bottom fet may be disabled at light loads by keeping s_mod low to trigger asynchronous operation, thus saving the bottom fet?s gate drive current and inductor ripple current. an inter- nal voltage reference allows threshold adjustment for an output over-voltage protection circuitry, independent of the pwm controller. the device provides overvoltage protection independant of the pwm feedback loop with a unique ?adaptive ovp? comparator which rejects noise but responds quickly to a true ovp situation. under-voltage-lock-out circuit is included to guarantee that both driver outputs are off when vcc is less than or equal to 4.4v (typ) at supply ramp up (4.35v at supply ramp down). a cmos output provides status indication of the 5v supply. a low enable input places the ic in stand- by mode, reducing supply current to less than 10a. sc1405c is offered in a high pitch (.025? lead spacing) tssop package. ? fast rise and fall times (15ns with 3000pf load) ? 14ns max. propagation delay (bg going with low) ? adaptive and programmable shoot-through protection ? adaptive overvoltage protection ? wide input voltage range (4.5-25v) ? programmable delay between mosfet?s ? power saving asynchronous mode control ? output overvoltage protection/overtemp shutdown ? under-voltage lock-out and power ready signal ? less than 10a stand-by current (en=low) ? power ready output signal ? high frequency (to 1.2mhz) operation allows use of small inductors and low cost caps in place of electrolytics ? high density/fast transient microprocessor power supplies ? motor drives/class-d amps ? high efficiency portable computers sc1406g imvp controller sc1406g imvp controller vid [4:0] vid [4:0] sc1405 smart mosfet driver sc1405 smart mosfet driver lo +vcc_cpu_core +vcc_cpu_core co 3.3v +vcc_cpu_io +vcc_cpu_io +vcc_cpu_clk +vcc_cpu_clk 1.5v 2.5a 2.5v 150ma +v_in +v_5 3.3v 0.925v-2.0v up to 14a ldo controller ldo controller pwm controller sc1406g imvp controller sc1406g imvp controller vid [4:0] vid [4:0] sc1405 smart mosfet driver sc1405 smart mosfet driver lo +vcc_cpu_core +vcc_cpu_core co 3.3v +vcc_cpu_io +vcc_cpu_io +vcc_cpu_clk +vcc_cpu_clk 1.5v 2.5a 2.5v 150ma +v_in +v_5 3.3v 0.925v-2.0v up to 14a ldo controller ldo controller pwm controller
2 ? 2004 semtech corp. www.semtech.com power management sc1405c absolute maximum ratings r e t e m a r a pl o b m y ss n o i t i d n o cm u m i n i mm u m i x a ms t i n u v c c e g a t l o v y l p p u sv x a m c c 3 . 0 -7v d n g p o t t s bx a m v d n g p - t s b 3 . 0 -0 3v n r d o t t s bx a m v n r d - t s b 3 . 0 -7v d n g p o t n r dx a m v n g p - n r d c d2 -5 2v d n g p o t n r dx a m v n g p - n r d s n 0 0 1 , t n e i s n a r t4 -5 2v d n g p o t s _ p v ox a m v d n g p - s p v o 3 . 0 -0 1v , y d r p , e d o m , s p s d , o c , n e d n g a o t y a l e d 3 . 0 -v c c 3 . 0 +v d n g p o t d n g a 1 -1 +v n o i t a p i s s i d r e w o p s u o u n i t n o cd pt , c 5 2 = b m a t j c 5 2 1 = t , c 5 2 = e s a c t j c 5 2 1 = 6 6 . 0 6 5 . 2 ? e s a c o t n o i t c n u j e c n a d e p m i l a m r e h t c j 0 4w / c o t n o i t c n u j e c n a d e p m i l a m r e h t t n e i b m a a j 0 5 1w / c e g n a r e r u t a r e p m e t g n i t a r e p ot j 05 2 1 +c e g n a r e r u t a r e p m e t e g a r o t st g t s 5 6 -0 5 1 +c . c e s 0 1 ) g n i r e d l o s ( e r u t a r e p m e t d a e lt d a e l 0 0 3c note: (1) specification refers to application circuit. unless specified: -0 < j < 125c; v cc = 5v; 4v < v bst < 26v electrical characteristics - dc operating specifications r e t e m a r a pl o b m y ss n o i t i d n o cn i mp y tx a ms t i n u y l p p u s r e w o p e g a t l o v y l p p u sv c c 5 . 45 0 . 6v t n e r r u c t n e c s e i u qy b t s _ q iv 0 = n e0 1a g n i t a r e p o , t n e r r u c t n e c s e i u qp o _ q iv c c v 0 = o c , v 5 =1a m y d r p e g a t l o v t u p t u o l e v e l h g i hv h o v c c a m 0 1 = d a o l l , v 6 . 4 =5 . 45 5 . 4v e g a t l o v t u p t u o l e v e l w o lv l o v c c , d l o h s e r h t o l v u < a 0 1 = d a o l l 1 . 02 . 0v t n e r r u c k n i si k n i s _ o v 4 . 0 = y d r p v50 1a m exceeding the specifications below may result in permanent damage to the device, or device malfunction. operation outside of th e parameters specified in the electrical characteristics section is not implied. 3 ? 2004 semtech corp. www.semtech.com power management sc1405c r e t e m a r a pl o b m y ss n o i t i d n o cn i mp y tx a ms t i n u r d _ s p s d e g a t l o v t u p t u o l e v e l h g i hv h o v c c f p 0 0 1 = d a o l c , v 6 . 4 =5 1 . 4v e g a t l o v t u p t u o l e v e l w o lv l o v c c f p 0 0 1 = d a o l c , v 6 . 4 =5 0 . 0v t u o k c o l e g a t l o v r e d n u d l o h s e r h t t r a t s 2 . 44 . 46 . 4v s i s e r e t s y hs y h v5 0 . 0v d l o h s e r h t e v i t c a c i g o lw o l s i n e5 . 1v n o i t c e t o r p e g a t l o v r e v o d l o h s e r h t p i r tv p i r t 5 4 1 . 12 . 15 5 2 . 1v s i s e r e t s y hs y h v p v o 8 . 0v e v i r d r e v o v m 0 5 , y a l e d p i r t5 2 1 o t 0 = t o c0 0 30 7 40 0 8s n v m 0 0 1 , y a l e d p i r t e v i r d r e v o 5 2 1 o t 0 = t o c5 2 15 2 20 0 4s n d o m _ s e g a t l o v t u p n i l e v e l h g i hv h i 0 . 2v e g a t l o v t u p n i l e v e l w o lv l i 8 . 0v e l b a n e e g a t l o v t u p n i l e v e l h g i hv h i 0 . 2v e g a t l o v t u p n i l e v e l w o lv l i 8 . 0v o c e g a t l o v t u p n i l e v e l h g i hv h i 0 . 2v e g a t l o v t u p n i l e v e l w o lv l i 8 . 0v n w o d t u h s l a m r e h t t n i o p p i r t e r u t a r e p m e t r e v ot p t o 5 6 1 o c s i s e r e t s y ht t s y h 0 1 o c r e v i r d e d i s - h g i h t n e r r u c t u p t u o k a e pi h k p 3 a e c n a t s i s e r t u p t u oc r s r g t k n i s r g t , s 0 0 1 < w p t , % 2 < e l c y c y t u d v , c 5 2 1 = j t t s b v - n r d , v 5 . 4 = v g t v + ) c r s ( v 0 . 4 = n r d n r d v + ) k n i s ( v 5 . 0 = g t v r o 1 7 . ? e v i r d e d i s - w o l t n e r r u c t u p t u o k a e pi l k p 3 a e c n a t s i s e r t u p t u oc r s r g b k n i s r g b , s 0 0 1 < w p t , % 2 < e l c y c y t u d , c 5 2 1 = j t v s v , v 6 . 4 = v g b ) c r s ( v 4 = v r o r d w o l ) k n i s ( v 5 . 0 = 2 . 1 0 . 1 ? electrical characteristics - dc operating specifications 4 ? 2004 semtech corp. www.semtech.com power management sc1405c electrical characteristics - ac operating specifications r e t e m a r a pl o b m y ss n o i t i d n o cn i mp y tx a ms t i n u r e v i r d e d i s h g i h e m i t e s i rr t 1 g t v , f n 3 = i c t s b v - n r d , v 6 . 4 =4 1 3 2 s n e m i t l l a ff t g t v , f n 3 = i c t s b v - n r d , v 6 . 4 =2 1 9 1 s n , e m i t y a l e d n o i t a g a p o r p h g i h g n i o g g t h d p t g t v , f n 3 = i c t s b v - n r d , v 6 . 4 = 0 = y a l e d - c 0 2 2 3 s n , e m i t y a l e d n o i t a g a p o r p w o l g n i o g g t l d p t g t v , f n 3 = i c t s b v - n r d , v 6 . 4 =5 1 4 2 s n r e v i r d e d i s - w o l e m i t e s i rr t g b v , f n 3 = i c s v , v 6 . 4 =5 1 4 2 s n e m i t l l a fr t g b v , f n 3 = i c s v , v 6 . 4 =3 1 1 2 s n , e m i t y a l e d n o i t a g a p o r p h g i h g n i o g g b h d p t i h g b v , f n 3 = i c t s b v - n r d , v 6 . 4 = 0 = y a l e d - c 2 1 9 1 s n , e m i t y a l e d n o i t a g a p o r p w o l g n i o g g t l d p t g b v , f n 3 = i c s v , v 6 . 4 = n r d 6 ? 2004 semtech corp. www.semtech.com power management sc1405c pin configuration ordering information pin descriptions top view (14-pin tssop) e c i v e d ) 1 ( e g a k c a pt ( e g n a r p m e t j ) r t . s t c 5 0 4 1 c s4 1 - p o s s tc 5 2 1 o t 0 note: (1) only available in tape and reel packaging. a reel contains 2500 devices. # n i pe m a n n i pn o i t c n u f n i p 1s _ p v o n o i t c e t o r p t e s o t d e r i u q e r s r o t s i s e r g n i l a c s l a n r e t x e . e s n e s n o i t c e t o r p e g a t l o v r e v o . d l o h s e r h t 2n e d n a , g b , g t , w o l n e h w . e c i v e d e h t f o y r t i u c r i c l a n r e t n i e h t s e l b a n e n i p s i h t , h g i h n e h w . a 0 1 n a h t s s e l s i ) v 5 ( t n e r r u c y l p p u s e h t d n a w o l d e c r o f e r a y d r p 3d n g. d n g c i g o l 4o c. s r e v i r d t e f s o m e h t o t l a n g i s t u p n i l e v e l - l t t 5d o m _ s n e h w . n o i t a r e p o s u o n o r h c n y s a g n i r e g g i r t , w o l e b o t g b s e c r o f l a n g i s s i h t , w o l n e h w . l a n g i s s i h t f o n o i t c n u f a t o n s i g b , h g i h 6c _ y a l e d n o i t a g a p o r p l a n o i t i d d a e h t s t e s d n g d n a n i p s i h t n e e w t e b d e t c e n n o c e c n a t i c a p a c e h t o n f i . f p / s n 1 + s n 0 2 = y a l e d n o i t a g a p o r p l a t o t . h g i h g n i o g g t o t w o l g n i o g g b r o f y a l e d . s n 0 2 = y a l e d n o i t a g a r p o r p e h t , d e t c e n n o c s i r o t i c a p a c 7y d r p s i h t , d l o h s e r h t o l v u e h t n a h t s s e l s i c c v n e h w . c c v f o s u t a t s e h t s e t a c i d n i n i p s i h t s i h t d l o h s e r h t o l v u e h t o t s l a u q e r o n a h t r e t a e r g s i c c v n e h w . w o l n e v i r d s i t u p t u o . h g i h s e o g t u p t u o 8c c v o t c c v m o r f d e t c e n n o c e b d l u o h s r o t i c a p a c c i m a r e c f 1 - 2 2 . a . v 8 - 5 f o y l p p u s t u p n i . p i h c e h t o t e s o l c y r e v d n g p 9g b. t e f s o m ) m o t t o b ( s u o n u o r h c n y s e h t r o f e v i r d t u p t u o 0 1d n g p . ) d n u o r g r e w o p ( n i p e c r u o s t e f s u o n o r h c n y s e h t o t t c e n n o c . d n u o r g r e w o p 1 1r d _ s p s d n i p s i h t , h g i h s i d o m - s n e h w . l a n g i s t u p t u o l e v e l l t t . e v i r d h c t i w s t n i o p t e s c i m a n y d . e g a t l o v n i p r e v i r d g b e h t s w o l l o f 2 1n r d n i p s i h t . s ' t e f s o m s u o n o r h c n y s d n a g n i h c t i w s e h t f o n o i t c n u j e h t o t s t c e n n o c n i p s i h t . n o i t a r e p o g n i t c e f f a t u o h t i w d n g p o t e v i t a l e r m u m i n i m v 2 - a o t d e t c e j b u s e b n a c 3 1g t. t e f s o m ) e d i s - h g i h ( g n i h c t i w s e h t r o f e v i r d e t a g t u p t u o 4 1t s b e h t p o l e v e d o t s n i p n r d d n a t s b n e e w t e b d e t c e n n o c s i r o t i c a p a c a . n i p p a r t s t o o b y l l a c i p y t s i e u l a v r o t i c a p a c e h t . t e f s o m e d i s - h g i h e h t r o f e g a t l o v p a r t s t o o b g n i t a o l f . ) c i m a r e c ( f 1 d n a f 1 . 0 n e e w t e b note: note: note: note: note: (1) all logic level inputs and outputs are open collector ttl compatible. 7 ? 2004 semtech corp. www.semtech.com power management sc1405c block diagram applications information sc1405c sc1405c sc1405c sc1405c sc1405c is designed to drive low rds_on power mosfet?s with ultra-low rise/fall times and propagation delays. as the switching frequency of pwm controllers is increased to reduce power supply volume and cost, fast rise and fall times are necessary to minimize switching losses (top mosfet) and reduce dead-time (bottom mosfet) losses. while low rds_on mosfet?s present a power saving in i 2 r losses, the mosfet?s die area is larger and thus the effective input capacitance of the mosfet is increased. often a 50% decrease in rds_on more than doubles the effective input gate charge, which must be supplied by the driver. the rds_on power sav- ings can be offset by the switching and dead-time losses with a suboptimum driver. while discrete solution can achieve reasonable drive capability, implementing shoot- through, programmable delay and other housekeeping functions necessary for safe operation can become cum- bersome and costly. the sc1405 family of parts pre- sents a total solution for the high-speed, high power den- sity applications. wide input supply range of 4.5v-25v allows use in battery powered applications, new high volt- age, distributed power servers as well as class-d ampli- fiers. theory of operation the control input (co) to the sc1405c is typically sup- plied by a pwm controller that regulates the power sup- ply output. (see application evaluation schematic, fig- ure 3). the timing diagram demonstrates the sequence of events by which the top and bottom drive signals are applied. the shoot-through protection is implemented by holding the bottom fet off until the voltage at the phase node (intersection of top fet source, the output inductor and the bottom fet drain) has dropped below 1v. this assures that the top fet has turned off and that a direct current path does not exist between the input supply and ground, a condition which both the top and bottom fet?s are on momentarily. the top fet is also prevented from turning on until the bottom fet is off. this time is internally set to 20ns (typical) and may be increased by adding a capacitor from the c-delay pin to gnd. the delay is approximately 1ns/pf in addition to the internal 20ns delay. the external capacitor may be needed if multiple high input capacitance mosfet?s are used in parallel and the fall time is substantially greater than 20ns. it must be noted that increasing the dead-time by high values of c-delay capacitor will reduce efficiency since the parallel schottky or the bottom fet body diode will have to conduct during dead-time. layout guidelines as with any high speed , high current circuit, proper lay- out is critical in achieving optimum performance of the sc1405c. the evaluation board schematic (refer to figure 3) shows a dual phase synchronous design with all surface mountable components. while components connecting to c-delay, ovp_s, en,s- 8 ? 2004 semtech corp. www.semtech.com power management sc1405c mod, dsps_dr and prdy are relatively noncritical, tight placement and short, wide traces must be used in layout of the drives, drn, and especially pgnd pin. the top gate driver supply voltage is provided by bootstrapping the +5v supply and adding it the phase node voltage (drn). since the bootstrap capacitor supplies the charge to the top gate, it must be less than .5? away from the sc1405. ceramic x7r capacitors are a good choice for supply bypassing near the chip. the vcc pin capacitor must also be less than .5? away from the sc1405. the ground node of this capacitor, the sc1405 pgnd pin and the source of the bottom fet must be very close to each other, preferably with common pcb copper land and multiple vias to the ground plane (if used). the par- allel schottky (if used) must be physically next to the bottom fets drain and source. any trace or lead induc- tance in these connections will drive current way from the schottky and allow it to flow through the fet?s body diode, thus reducing efficiency. preventing inadvertent bottom fet turn-on at high input voltages, (12v and greater) a fast turn-on of the top fet creates a positive going spike on the bot- tom fet?s gate through the miller capacitance, crss of the bottom fet. the voltage appearing on the gate due to this spike is: vspike= vin*crss (crass+ciss) where ciss is the input gate capacitance of the bottom fet. this is assuming that the impedance of the drive path is too high compared to the instantaneous imped- ance of the capacitors. (since dv/dt and thus the effec- tive frequency is very high). if the bg pin of the sc1405c is very close to the bottom fet, vspike will be reduced depending on trace inductance, rate if rise of current, etc. while not shown in figure 3, a capacitor may be added from the gate of the bottom fet to its source, preferably less than .5? away. this capacitor will be added to ciss in the above equation to reduce the effective spike volt- age, vspike. the selection of the bottom mosfet must be done with attention paid to the crss/ciss ratio. a low ratio reduces applications information the miller feedback and thus reduces vspike. also mosfets with higher turn-on threshold voltages will con- duct at a higher voltage and will not turn on during the spike. the mosfet shown in the schematic has a 2 volt threshold and will require approximately 5 volts vgs to be conducting, thus reducing the possibility of shoot-through. a zero ohm bottom fet gate resistor will obviously help keeping the gate voltage low. ultimately, slowing down the top fet by adding gate re- sistance will reduce di/dt which will in turn make the ef- fective impedance of the capacitors higher, thus allow- ing the bg driver to hold the bottom gate voltage low. ringing on the phase node the top mosfet source must be close to the bottom mosfet drain to prevent ringing and the possibility of the phase node going negative. this frequency is deter- mined by: 1 f ring = (2 * sqrt(l st *coss)) where: l st = the effective stray inductance of the top fet added to trace inductance of the connection between top fet?s source and the bottom fet?s drain added to the trace resistance of the bottom fet?s ground connection. coss=drain to source capacitance of bottom fet. if there is a schottky used, the capacitance of the schottky is added to the value. although this ringing does not pose any power losses due to a fairly high q, it could cause the phase node to go too far negative, thus causing improper operation, double pulsing or at worst driver damage. this ringing is also an emi nuisance due to its high resonant frequency. adding a capacitor, typically 1000-2000pf, in parallel with coss can often eliminate the emi issue. if double puls- ing is caused due to excessive ringing, placing 4.7-10 ohm resistor between the phase node and the drn pin of the sc1405 should eliminate the double pulsing. the negative voltage spikes on the phase node adds to the bootstrap capacitor voltage, thus increasing the volt- age between vbst - vdrn. if the phase node negative 9 ? 2004 semtech corp. www.semtech.com power management sc1405c spikes are too large, the voltage on the boost capacitor could exceed device?s absolute maximum rating of 8v. to eliminate the effect of the ringing on the boost ca- pacitor voltage, place a 4.7 - 10 ohm resistor between boost schottky diode and vcc to filter the negative spikes on drn pin. alternately, a silicon diode, such as the commonly available 1n4148 can substitute for the schottky diode and eliminate the need for the series re- sistor. proper layout will guarantee minimum ringing and elimi- nate the need for external components. use of so-8 or other surface mount mosfets will reduce lead induc- tance and their parasitic effects. asynchronous operation the sc1405c can be configured to operate in asynchro- nous mode by pulling s-mod to logic low, thus disabling the bottom fet drive. this has the effect of saving power at light loads since the bottom fet?s gate capacitance does not have to charged at the switching frequency. there can be a significant savings since the bottom driver can supply up to 2a pulses to the fet at the switching frequency. there is an additional efficiency benefit to operating in asynchronous mode. when operating in syn- chronous mode, the inductor current can go negative and flow in reverse direction when the bottom fet is on and the dc load is less than 1/2 inductor ripple current. at that point, the inductor core and wire losses, depend- ing on the magnitude of the ripple current, can be quite significant. operating in asynchronous mode at light loads effectively only charges the inductor by as much as needed to supply the load current, since the inductor never completely discharges at light loads. dc regula- tion can be an issue when operating in asynchronous mode, depending on the type of controller used and mini- mum load required to maintain regulation. if there are no shottkey diodes used in parallel with bottom fet, the fet?s body diode will need to conduct in asynchronous mode. the high voltage drop of this diode must be con- sidered when determining the criteria for this mode of operation. applications information (cont.) dsps dr this pin produces an output which is a logical duplicate of the bottom fet?s gate drive, if s-mod is held low. ovp_s/over temp shutdown output over-voltage protection (ovp) may be implemented on the sc1405c independent of the pwm controller . a voltage divider from the output is compared with the in- ternal bandgap voltage of 1.2v (typical). upon exceeding this voltage, the overvoltage comparator disables the top fet, while turning on the bottom fet to allow discharge of the output capacitors excessive voltage through the output inductor. the sc1405c has a unique adaptive ovp circuit. short noise pulses, less than ~100ns are rejected completely; longer pulses will trigger ovp if only of sufficient magni- tude. a long term transient will trigger ovp with a smaller magnitude. to assure proper tripping, bypass the resis- tor from ovp_s pin to gnd with a capacitor. the value of this capacitor must be selected to achieve a time con- stant equal to one switching period. leave at least 250mv headroom on the ovp pin to prevent false ovp events. the sc1405c will shutdown if its t j exceeds 165c. 10 ? 2004 semtech corp. www.semtech.com power management sc1405c pin descriptions typical characteristics performance diagrams, application evaluation board. pin descriptions timing diagram: ch1: co input ch2: tg drive ch3: bg non-overlap drive ch4: phase node iout = 20a (10a/phase) refer to eval. schematic (fig.3) timing diagram: rise/fall times ch1: tg drive ch2: bg drive cursor: tpdh tg iout = 20a (10a/phase) refer to eval. schematic (fig.3) v in = 12v, v out = 1.6v. top fet = ir7811 fdb7030(bl) qgd = 23nc 11 ? 2004 semtech corp. www.semtech.com power management sc1405c typical characteristics (cont.) sc1405c ovp delay vs. temperature 0.00 100.00 200.00 300.00 400.00 500.00 600.00 -25-51535557595115135 temperature (c) delay (ns) 50mv overdrive 100mv overdrive typical delay vs. overdrive (t=25c) 100 1000 10000 10 1000 overdrive (mv) delay (ns) delay vs. temp. delay vs. overdrive 12 ? 2004 semtech corp. www.semtech.com power management sc1405c evaluation board schematic figure 3 - application evaluation board schematic 13 ? 2004 semtech corp. www.semtech.com power management sc1405c semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805)498-2111 fax (805)498-3804 outline drawing -tssop-14 contact information land pattern - tssop-14 |
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